Prof. Dr. Frank Bellosa

Daniel Habicht

Abstract
Todays high performance computing requires large memory capacities with low latency. These requirements can be fullfilled by using memory tiering solutions to optimize the latency of heterogenous memory systems, that solve the need for more memory capacity. Memory management strategies like memory tiering and Transparent DAX Mappings (TDM), which make direct access (DAX) mappings accessable for unaltered applications, rely on monitoring access frequency of data to determine whether to promote or demote said data to memory with less or more latency. Previous work that monitored the access frequency of data based on features of the operating system or the CPU show a trade-of between accuracy and performance impact, which we eliminate by using hardware-assisted bandwidth measurements of a custom FPGA-based Compute Express Link memory expander. Our implementation extends the Linux kernel to monitor the bandwidth for memory mappings and provide an interface of bandwidth measurements for monitored memory mapping to the userspace. To evaluate our approach, we implement a memory tiering application which promotes memory mappings to a fitting memory tier based on the measured bandwidth. We measured that our bandwidth measurement closely matches the actual bandwidth. Our memory tiering application uses these measurements to select the most fitting memory tier, which optimizes the overall bandwidth to beat just using the hot tier by 21% and interleaving each memory mapping across multiple memory tiers by 8%. We show that our bandwidth monitoring for memory mapping can be of advantage for applications like memory tiering.

BibTex:

@bachelorthesis{beckmann26CXLMemoryDevices,
  author = {Gero Beckmann},
 title = { Fine-Grained Bandwidth Monitoring for CXL Memory Devices },
  type = {Bachelor Thesis},
  year = 2026,
  month = jul# "27",
  school = {Operating Systems Group, Karlsruhe Institute of Technology (KIT), Germany}
  }