Compute Express Link
Compute Express Link (CXL) is a recent interconnect standard for communication between a CPU and periphery hardware. Based on the physical layer of PCI Express, CXL introduces three new protocols (CXL.io, CXL.mem, CXL.cache) to enable cache-coherent, byte-granular, and synchronous access (i.e., memory semantics) to attached devices. Commercially established use cases currently include DRAM-based memory expansion, memory pooling, and memory sharing.
CXL-related research at our group has two focus areas: First, memory management for CXL-based memory architectures, and second, the design of CXL-based hybrid SSDs and potential use cases for these. For the latter, we propose OS abstractions and resource management mechanisms as well as a novel approach to system suspend.
Our group is actively working on developing custom in-house FPGA-based CXL hardware prototypes, including a memory expander with enhanced reporting capabilities for memory management as well as a hybrid SSD prototype designed as a puzzle piece of our holistic hardware/software co-design approach for CXL-based storage. Learn more about how we leverage our home-grown hardware designs on the following pages.
Subprojects
Memory Management for CXL-Based Memory Architectures
CXL enables heterogeneous memory architectures composed of a diverse set of memory devices, each with distinct performance characteristics. To achieve fair resource allocation between tasks while also avoiding situations where oversaturated memory devices slow down execution, system software must be aware of these differences and carefully manage memory resources. Learn more about how we use a custom scheduler for enforcing per-process bandwidth limits efficiently, to provide a practical trade-off between throughput, tail latency, and CPU utilization.
We define a CXL-based hybrid SSD as a NAND-based storage device with a DRAM cache that features both a traditional asynchronous and block-addressable DMA interface for host communication as well as a CXL-based interface that is synchronous and byte-addressable. This raises the fundamental questions of how and when to use which interface for maximum performance and energy benefit and how to manage the device and its cache. Learn more about our ongoing research efforts in this area.
Fast and Power-Efficient System Suspend
Traditionally, system suspend mechanisms offer a trade-off between energy efficiency and resume times. Users either get fast resume at the expense of higher energy consumption while suspended or zero energy consumption at the expense of a longer resume duration. In our research, we try to combine best of both worlds, aiming to achieve a zero-power suspend mechanism that offers fast resume nonetheless. Learn more about how we are working to achieve this goal by leveraging CXL-based hybrid SSDs in a co-design approach that encompasses both system firmware as well as the operating system.