ITEC -  Operating Systems Group

Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor

  • Author:

    Adam Wiggins, Harvey Tuch, Volkmar Uhlig, and Gernot Heiser

  • Source:

    Proceedings of the Eighth Asia-Pacific Computer Systems Architecture Conference (ACSAC'03), Aizu-Wakamatsu City, Japan, September 23-26, 2003

  • Date: 23.-26.09.2003
  • Abstract:

    The StrongARM processor features virtually-addressed caches and a TLB without address-space tags. A naive implementation therefore requires ushing of all CPU caches and the TLB on each context switch, which is very costly. We present an implementation of fast context switches on the architecture in both Linux and the L4 microkernel. It is based on using domain tags as address-space identi ers and delaying cache ushes until a clash of mappings is detected. We observe a reduction of the context-switching overheads by about an order of magnitude compared to the naive scheme presently implemented in Linux.

    We also implemented sharing of TLB entries for shared pages, a natural extension of the fast-context-switch approach. Even though the TLBs of the StrongARM are quite small and a potential bottleneck, we found that bene ts from sharing TLB entries are generally marginal, and can only be expected to be signi cant under very restrictive conditions.


      author = {Adam Wiggins and Harvey Tuch and Volkmar Uhlig and Gernot Heiser},
      title =  {Implementation of Fast Address-Space Switching and TLB Sharing on the StrongARM Processor},
      booktitle = {Proceedings of the 8th Asia-Pacific Computer Systems Architecture Conference},
      address = {Aizu-Wakamatsu City, Japan},
      month = sep # "~23--26",
      year = 2003