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Power Management

With the emergence of portable and wireless devices and with the thermal problems originating from high-power processors we are facing a rising awareness for the topic of dynamic energy management.

The interface between the hardware, whose energy consumption should be controlled, and the application software, which consumes energy implicitly by activating hardware components, is the operating system. Because of the operating system's role as a mediator, it is predestined for any kind of resource accounting. This includes the aspect of energy as an indispensible first class resource.

Server Power Management

Our research on server power management is driven by the need for reducing thermal problems and the need for making efficient use of energy. We concentrate on the processor as a resource consuming major amounts of energy and suffering severely from thermal problems.

With the introduction of on-chip thread-level parallelism (simultaneous multithreading and chip multiprocessing) in recent microprocessor generations, contention for processor resources has become an issue. With multiple threads of execution running in parallel on a chip, shared resources, i.e., functional units such as integer or floating point units, caches or the memory interface, can become a bottleneck, if tasks utilizing the resources heavily are executed at the same time, resulting in poor use of energy.

Apart from this, increasing circuit density and power consumption has made power an additional resource, in the sense that only a limited amount of thermal energy can be removed from the chip in a certain period of time lest the chip overheat and suffer malfunction or even permanent damage. Since power dissipation is caused by activity on the chip, the resource power is inherently coupled to the utilization of the functional units on the chip.

Utilization of chip resources is a characteristic of a specific application and varies between different applications. The operating system scheduler—managing the running applications (tasks)—can take great influence on resource contention and temperature by virtue of its scheduling decisions, i.e., by deciding which tasks to run at what time and in combination with which other tasks. Schedulers found in today's general purpose operating systems are unaware of the utilization of chip resources caused by the tasks they manage. This leads to sub-optimal scheduling decisions causing contention, thermal problems and, overall, inefficient use of the processor's resources.

We have shown that event-driven, temperature-aware scheduling can balance the temperature between different physical processors guided by a characterization of tasks by their power consumption. However, tackling thermal imbalances between functional units within a chip, as well as dealing with resource contention, requires a more detailed characterization of tasks.

As a novel metric to guide temperature-aware and energy-efficient scheduling, we have proposed task activity vectors. An activity vector provides information to the scheduler about which CPU resources a particular task uses. The scheduler can use this knowledge to make more informed scheduling decisions and use the chip's resources more efficiently.

We have investigated two possible applications of activity vectors. Firstly, we have shown that the information provided by activity vectors can be used to attain a more balanced temperature distribution on the chip and avoid dangerous hotspots by controlling the order in which tasks are scheduled. Secondly, we have shown that activity vectors are suitable for co-scheduling tasks in a way that avoids resource contention and uses the processor in a more energy-efficient manner.

Author Title Source

Andreas Merkel and Frank Bellosa

Proceedings of the First ACM SIGOPS EuroSys Conference, Leuven, Belgium, April 18-21, 2006

Andreas Merkel, Frank Bellosa and Andreas Weissel

Second Workshop on Temperature-Aware Computer Systems (TACS'05), Juni 2005 in Madison, USA

Andreas Merkel and Frank Bellosa

Third ACM SIGOPS EuroSys Conference, Glasgow, Scotland, March 31 - April 4, 2008

Andreas Merkel and Frank Bellosa

Proceedings of the Workshop on Power Aware Computing and Systems (HotPower'08), San Diego, CA, December 7, 2008

Andreas Merkel, Jan Stoess, and Frank Bellosa

Proceedings of the 5th ACM SIGOPS EuroSys Conference (EurosSys'10), Paris, France, April 2010



I/O Power Management

Cooperative I/O

We demonstrate the benefits of application involvement in operating system power management. We present Coop-I/O, an approach to reduce the power consumption of devices while encompassing all levels of the system-from the hardware and OS to a new interface for cooperative I/O that can be used by energy-aware applications.

We assume devices which can be set to low-power operation modes if they are not accessed and where switching between modes consumes additional energy, e.g. devices with rotating components or network devices consuming energy for the establishment and shutdown of network connections. In these cases frequent mode switches should be avoided.

With Coop-I/O, applications can declare open, read and write operations as deferrable and even abortable by specifying a time-out and a cancel flag. This information enables the operating system to delay and batch requests so that the number of power mode switches is reduced and the device can be kept longer in a low-power mode.

We will show that in many cases Coop-I/O even outperforms the "oracle" shutdown policy which defines the lower bound in power consumption if the timing of requests cannot be influenced.

Author Title Source

Andreas Weißel, Björn Beutel, and Frank Bellosa

Proceedings of the Fifth Symposium on Operating Systems Design and Implementation (OSDI '02), Boston, MA, December 9-11, 2002



Wireless Network Power Management

 

This approach identifies on-line the currently running application class by a mapping of network traffic characteristics to a predefined set of application profiles.

We propose a power saving policy which dynamically adapts the sleep interval of an IEEE 802.11 network interface to the detected application profile according to application- and user-specific power/performance demands.

Author Title Source

Andreas Weißel, Matthias Faerber, and Frank Bellosa

Proceedings of the International Conference on Architecture of Computing Systems (ARCS'04), Augsburg, Germany, March 23-26, 2004



Frequency Scaling

Process Cruise Control

Scalability of the core frequency is a common feature of low-power processor architectures. Many heuristics for frequency scaling were proposed in the past to find the best trade-off between energy efficiency and computational performance. With complex applications exhibiting unpredictable behavior these heuristics cannot reliably adjust the operation point of the hardware because they do not know where the energy is spent and why the performance is lost.

Embedded hardware monitors in the form of event counters have proven to offer valuable information in the field of performance analysis. We will demonstrate that counter values can also characterize the power-specific characteristics of a thread.

We propose an energy-aware scheduling policy that benefits from event counters. By exploiting the information from these counters, the scheduler determines the appropriate clock frequency for each individual thread running in a time-sharing environment. A recurrent analysis of the thread-specific energy and performance profile allows an adjustment of the frequency to the behavioral changes of the application. While the clock frequency may vary in a wide range, the application performance should only suffer slightly (e.g. with 10% performance loss compared to the execution at the highest clock speed). Because of the similarity to a car cruise control, we called our scheduling policy Process Cruise Control. This adaptive clock scaling is accomplished by the operating system without any application support.

Process Cruise Control has been implemented on the Intel XScale architecture, that offers a variety of frequencies and a set of configurable event counters. Energy measurements of the target architecture under variable load show the advantage of the proposed approach.

Author Title Source

Andreas Weißel and Frank Bellosa

Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES 2002), Grenoble, France, October 8-11 2002