Server Power Management
Our research on server power management is driven by the need for reducing thermal problems and the need for making efficient use of energy. We concentrate on the processor as a resource consuming major amounts of energy and suffering severely from thermal problems.
With the introduction of on-chip thread-level parallelism (simultaneous multithreading and chip multiprocessing) in recent microprocessor generations, contention for processor resources has become an issue. With multiple threads of execution running in parallel on a chip, shared resources, i.e., functional units such as integer or floating point units, caches or the memory interface, can become a bottleneck, if tasks utilizing the resources heavily are executed at the same time, resulting in poor use of energy.
Apart from this, increasing circuit density and power consumption has made power an additional resource, in the sense that only a limited amount of thermal energy can be removed from the chip in a certain period of time lest the chip overheat and suffer malfunction or even permanent damage. Since power dissipation is caused by activity on the chip, the resource power is inherently coupled to the utilization of the functional units on the chip.
Utilization of chip resources is a characteristic of a specific application and varies between different applications. The operating system scheduler—managing the running applications (tasks)—can take great influence on resource contention and temperature by virtue of its scheduling decisions, i.e., by deciding which tasks to run at what time and in combination with which other tasks. Schedulers found in today's general purpose operating systems are unaware of the utilization of chip resources caused by the tasks they manage. This leads to sub-optimal scheduling decisions causing contention, thermal problems and, overall, inefficient use of the processor's resources.
We have shown that event-driven, temperature-aware scheduling can balance the temperature between different physical processors guided by a characterization of tasks by their power consumption. However, tackling thermal imbalances between functional units within a chip, as well as dealing with resource contention, requires a more detailed characterization of tasks.
As a novel metric to guide temperature-aware and energy-efficient scheduling, we have proposed task activity vectors. An activity vector provides information to the scheduler about which CPU resources a particular task uses. The scheduler can use this knowledge to make more informed scheduling decisions and use the chip's resources more efficiently.
We have investigated two possible applications of activity vectors. Firstly, we have shown that the information provided by activity vectors can be used to attain a more balanced temperature distribution on the chip and avoid dangerous hotspots by controlling the order in which tasks are scheduled. Secondly, we have shown that activity vectors are suitable for co-scheduling tasks in a way that avoids resource contention and uses the processor in a more energy-efficient manner.
Contact: Prof. Dr.-Ing. Frank Bellosa
Author | Title | Source |
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Andreas Merkel and Frank Bellosa |
Balancing Power Consumption in Multiprocessor Systems | Proceedings of the First ACM SIGOPS EuroSys Conference, Leuven, Belgium, April 18-21, 2006 |
Andreas Merkel and Frank Bellosa |
Memory-aware Scheduling for Energy Efficiency on Multicore Processors | Proceedings of the Workshop on Power Aware Computing and Systems (HotPower'08), San Diego, CA, December 7, 2008 |
Andreas Merkel and Frank Bellosa |
Task Activity Vectors: A New Metric for Temperature-Aware Scheduling | Third ACM SIGOPS EuroSys Conference, Glasgow, Scotland, March 31 - April 4, 2008 |
Andreas Merkel, Frank Bellosa and Andreas Weissel |
Event-Driven Thermal Management in SMP Systems | Second Workshop on Temperature-Aware Computer Systems (TACS'05), Juni 2005 in Madison, USA |
Andreas Merkel, Jan Stoess, and Frank Bellosa |
Resource-conscious Scheduling for Energy Efficiency on Multicore Processors | Proceedings of the 5th ACM SIGOPS EuroSys Conference (EurosSys'10), Paris, France, April 2010 |