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Lazy Context Switching Algorithms for Sparc-like Processors

Lazy Context Switching Algorithms for Sparc-like Processors
Author:

Jochen Liedtke

Links:
Source:

GMD Technical Report No. 776, September 1993

Date: 09.1993

Abstract:

Recent experiences show that inter-process communication (ipc) can be implemented very fast and efficiently. The necessary context switching basically consists of changing the address space and saving/restoring the processor's registers. This may become a performance bottleneck on processors with a large number of registers. For example, ipc would be 5 times slower on a Sparc processor than on a comparable 8-register processor, if all 136 Sparc registers are saved and restored on context switch.

Therefore, we propose to delay saving and restoring most registers until they are accessed (hoping that they are not accessed until the next process switch occurs).

This paper presents lazy context switching algorithms and tuning options on an abstract level. It is shown that on this level they do never perform worse and often better than existing algorithms. There are situations in which they need only about 4 memory references per context switch.

Since real life performance of these algorithms will heavily depend on coding, integration into an OS kernel and RPC profile, this paper can only be a basis for further experiments.

BibTex:

@TechReport{Liedtke93LazyContextSwitching,
  author = {Jochen Liedtke},
  title = {Lazy Context Switching Algorithms for Sparc-like Processors},
  booktitle = {GMD Technical Report},
  number = {776},
  month = sep,
  year = 1993,
  url = {http://l4ka.org/publications/}
}